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Detailed Description
Digitally Controlled Impedance (DCI)
Some FPGA banks can support the DCI feature in Virtex-4 FPGAs. Support for DCI is
summarized in Table 1-2 .
Table 1-2:
DCI Capability of FPGA Bank
FPGA Bank
1
2
3
4
5
6
7
8
DCI Capability
Not supported.
Not supported.
Optional: User must remove resistors R234 and R235 and must install
resistors R222 and R221. (1)
Not supported.
Optional: User must install resistors R224 and R225 to use DCI. In bitgen,
the switch "-g DCIUpdateMode:Quiet" must also be used. (2)
Not supported.
Optional: User must install resistors R289 and R290. (3)
Yes, 49.9 Ω resistors are installed.
Notes:
1. Use of DCI disables the use of GPIO LED [2] and [3].
2. Use of DCI disables user control of the DDR_CS_N and DDR_CKE signals.
3. This disables the use of two I/O pins on the expansion connector J5 (pin 38 and 40).
2. DDR SDRAM
The board contains 128 MB of DDR SDRAM divided between two Infineon
HYB25D512160BT-5 (or compatible) devices (U4 and U5). Each device is 16 bits wide and
together form a 32-bit data bus capable of running up to 400 MHz. All DDR SDRAM
signals are terminated through 47 Ω resistors to a 1.25V VTT reference voltage. The board is
designed for matched length traces across all DDR control and data signals except clocks
and the DDR loop trace (see “DDR Clock Signal” and “DDR Loop Signal” ).
The board can support up to 256 MB of total DDR SDRAM memory if larger chips are
installed. An extra address pin is present on the board to support up to 1-Gb DDR chips.
DDR Clock Signal
The DDR clock signal is broadcast from the FPGA as a single differential pair that drives
both DDR chips. The delay on the clock trace is designed to match the delay of the other
DDR control and data signals. The DDR clock is also fed back to the FPGA to allow for
clock deskew using Virtex-4 DCMs. The board is designed so that the DDR clock signal
reaches the FPGA clock feedback pin at the same time as it arrives at the DDR chips.
DDR Loop Signal
The DDR loop signal is a trace that is driven and then received back at the FPGA with a
delay equal to the sum of the trace delays of the clock and DQS signals. This looped trace
can be used in high-speed memory controllers to help compensate for the physical trace
delays between the FPGA and DDR chips.
ML405 Evaluation Platform
UG210 (v1.5.1) March 10, 2008
www.xilinx.com
13
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